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A2HW: Algorithms and Architectures for Digital Computing (ICS901)
(ICS901/A2HW) High Level Synthesis of Digital Operators
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    • Presentation
      • Architecture for Digital Operators and Algorithms
      • Introduction to Digital SoC Integration
      • High Level Synthesis of Digital Operators

    High Level Synthesis of Digital Operators

    • Documents presented in class: HLS Synthesis Lecture
    • Lab 1: Intel HLS simple counter
    • Lab 2: Low pass filter with Avalon Stream interfaces
    • Lab 3: A Data Encryption Standard accelerator using an Avalon MM interface
    Télécom-Paris - Master ICS